![]() However, for low speed buses routed on PCBs, there is another solution: update outputs on the negative clock edge, and latch inputs on the positive edge. On integrated circuits, FPGAs, and high speed interconnects, this is handled by careful clock routing and detailed knowledge of the setup and hold times of the flip flops, as well as their propagation delay. ![]() Note that this problem is independent of the clock frequency, slowing down the clock doesn't fix it, only fixing the relative delays will help. If the clock has more delay (due to trace length or capacitive loading) than the signal, then the second flip-flop can miss the value. If both flip-flops update on a rising edge, then the second one will be sampling its input at the same time the first is updating the output. This is an issue when you have one flip-flop output driving the input of the next.
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